In the fabrication of semiconductor integrated circuit (IC) chips, it is frequently necessary to electrically isolate devices that are formed on the surface of the chip. There are various ways of doing this. A way is by using the well-known LOCOS (Local Oxidation Of Silicon) process, wherein the surface of the chip is masked with a relatively hard material such as silicon nitride and a thick oxide layer is grown thermally in an opening in the mask. Another way is to etch a trench in the silicon and then fill the trench with a dielectric material such as silicon oxide, also known as trench isolation. While both LOCOS and trench isolation can prevent unwanted surface conduction between devices, they do not facilitate complete electrical isolation.
Complete electrical isolation is necessary to integrate certain types of transistors including bipolar junction transistors and various metal-oxide-semiconductor (MOS) transistors including power DMOS transistors. Complete isolation is also needed to allow CMOS control circuitry to float to potentials well above the substrate potential during operation. Complete isolation is especially important in the fabrication of analog, power, and mixed signal integrated circuits.
Non-Isolated CMOS Fabrication and Construction
Conventional CMOS wafer fabrication, while offering high density transistor integration, does not facilitate compete electrical isolation of its fabricated devices. FIG. 1A for example illustrates a simplified cross sectional view of a prior-art twin-well CMOS 1. FIG. 1A illustrates the formation of N-well (NW) regions 4A and 4B and P-well (PW) regions 3A and 3B in P-type substrate 2 prior to transistor fabrication.
FIG. 1B illustrates a CMOS structure 10 after transistor formation including N-channel MOSFETs fabricated within P-well 3A, P-channel MOSFETs formed within N-well 4B, separated by intervening LOCOS field oxide layer 11. The combination of P-channel and N-channel MOSFETS, together constitute complementary MOS transistors, otherwise referred to as CMOS.
Within PW region 3A, N-channel MOSFETs are formed comprising shallow N+ source-drain implanted region 14 with lightly doped drain (LDD) 15, polysilicon gate 19, and P+ to PW contact region 13. Within NW region 4B, P-channel MOSFETs are formed comprising shallow P+ source-drain implanted region 17 with LDD 18, polysilicon gate 19, and N+ to NW contact region 12. The NW and PW regions are ion implanted, generally with a subsequent high-temperature diffusion to drive the dopant into the substrate to a greater depth than the implant. The depth of the wells is generally greater for higher-voltage devices, e.g. 12V, than for lower voltage CMOS, especially at 3.3V or lower.
The transistor packing density of CMOS structure 10 is largely limited by the area wasted by LOCOS oxide 11, which cannot be reduced to deep submicron dimensions without encountering numerous problems. Another limitation of CMOS structure 10 is its gate construction comprising doped polysilicon 19 without any overlying shunting metal. As transistors are scaled to smaller dimensions, the gate resistance contributes to slower switching speeds and increased propagation delays. The impact of this gate resistance practically limits CMOS scaling to gate dimensions in the 0.8 to 0.6 micron range.
In analog circuitry another major limitation of CMOS 10 is its lack of complete electrical isolation. As shown, PW region 3A is shorted to substrate 2. Since P-well 3A electrically forms the body (or back gate) of the NMOS transistors, and since P-type substrate 2 is necessarily biased to the most negative on-chip potential (herein referred to as “ground”), then the body connection of every N-channel transistor is biased to ground, limiting their useful operating voltage range and subjecting the N-channel MOSFETs to unwanted substrate noise.
For CMOS transistors with gate lengths of 0.35 microns or smaller, structure 80 shown in FIG. 2A represents a common prior art realization of CMOS. In this structure, LOCOS field oxide layer 11 has been replaced with dielectrically filled shallow trenches 81 having dimensions one half the minimum LOCOS size or less. The polysilicon gate includes a metal silicide (such as platinum-silicide) to reduce gate resistance. The metal strapped polysilicon sandwich is sometimes referred to as a polycide layer, a concatenation of polysilicon and silicide. Note that in CMOS structure 80, despite its capability for smaller devices and high integration densities, P-well 3A is still electrically shorted to P-type substrate 2.
N-channel MOSFET 25, shown in FIG. 1C in cross section, is one of the non-isolated N-channel devices of LOCOS type CMOS structure 10, including P-well 27 formed in P-type substrate 26, N+ implant region 33, gate-oxide 36 located above PW channel region 35, topped with polysilicon gate 38 and gate silicide 39. Lightly doped drain extension 34′ is self-aligned to gate 38 while N+ region 33 is self-aligned to sidewall spacer 37. Also in MOSFET 25, a single layer of metal interconnection 41 is also included for illustration purposes, although an integrated circuit may utilize from 2- to 10-layers of metal interconnection. Interconnect metal 41, typically an aluminum-copper or aluminum-copper-silicon alloy, contacts N+ region 33 through contact openings in inter-level dielectric (ILD) 32 and through thin barrier metal 40. The barrier metal, typically comprising titanium, platinum, or tungsten is introduced to prevent metal spikes (i.e. filaments) from alloying through the N+ to P-well junction during processing and shorting out the transistor's junctions.
Note the unique shaped oxide 31 has the appearance of a bird's head and extended beak, where the oxide thickness is graduated over a distance of several tenths of a micrometer. This shape results from stress existing between the silicon and an overlying silicon nitride layer used to locally prevent oxidation in the active device regions. As the field oxidation progresses, oxygen diffuses under the nitride mask lifting its edges to produce the uniquely characteristic shape. The bird's beak has several unfortunate effects for smaller transistors, affecting the transistor's threshold and gain, and wasting usable real estate. In some processes a P-type field dopant PFD 29 is introduced prior to LOCOS field oxidation to raise the field threshold and suppress surface leakage between any two adjacent N-type regions. An N-type field dopant NFD 30 may also be introduced in the field areas over N-well regions 28 to prevent parasitic leakages between adjacent P-type regions. The problem with both NFD and PFD regions is they diffuse too deep during field oxidation and can adversely impact a transistor's electrical characteristics, especially for deep submicron devices.
Another characteristic of P-well 27 is its non-Gaussian doping profile, especially in channel region 35. One possible doping profile along the vertical section line A-A′ is shown in dopant concentration graph 50 in FIG. 1D. As shown, the dopant concentration of PW 27, shown as curve 52, follows a Gaussian profile intersecting with the constant doping concentration of substrate 26, shown as horizontal line 51. Since both PW 27 and substrate 26 are P-type, no P-N junction exists where they meet, and the P-well is not isolated from the substrate. Peaks 53, 54, and 55 represent implanted P-type dopant located in the channel region to prevent bulk punch-through breakdown, to prevent sub-surface leakage, and to set the threshold voltage of the device respectively. The graph shown, however, represents an ideal one-dimensional doping profile and ignores the impact of lateral intrusion under the gate by field dopant or field oxide, both of which alter the two-dimensional and even three-dimensional doping profiles, often in adverse ways. Scaling the LOCOS to smaller dimensions of thinner final thicknesses is problematic since the shape of the bird's beak becomes sensitive to slight process variations.
N-channel MOSFET 100 shown in the cross section of FIG. 2B avoids the aforementioned LOCOS issues by replacing the field oxidation process with a dielectric filled trench 104. Methods for forming dielectrically-filled trench isolation regions are discussed in a related application Ser. No. 11/298,075, filed Dec. 9, 2005, titled “Isolation Structures for Semiconductor Integrated Circuit Substrates and Methods of Forming the same” by Richard K. Williams, which is incorporated herein by reference in its entirety. Without LOCOS, no bird's beak is present to encroach on polysilicon gate 113 or impact the doping of channel region 112, and device 100 can be scaled to smaller dimensions. Like its predecessors, N-channel MOSFET 100 is formed in P-well 102 which is electrically shorted to P-substrate 101 and does not provide electrical isolation.
FIG. 3A illustrates several common prior art process flows for fabricating non-isolated CMOS using LOCOS or trench isolation. Shown as a series of cards, those cards having square corners are mandatory processing steps while those with clipped corners (such as NFD implant) represent optional process steps.
FIG. 3B illustrates a schematic representation of a CMOS pair 130 comprising P-channel MOSFET 132 and N-channel MOSFET 131 and fabricated using either of the prior art fabrication sequences described. Each transistor includes four terminals—a source S, a drain D, a gate G and a body or back-gate B. In the case of P-channel MOSFET 132, its source-to-body junction is schematically represented as P-N diode 136, and its drain-to-body junction is illustrated by P-N diode 137. Resistance of the N-well region is illustrated as a lumped-circuit-element resistance 138, but in reality is spatially distributed across the device, especially for large area power devices.
One weakness of P-channel 132 is that it inherently includes a substrate-PNP 139, parasitic to the device's construction. As shown, with the source acting as an emitter injecting holes into the N-well base, some fraction of those holes may penetrate the N-well base without recombining and may ultimately be collected by the substrate as hole current. If the gain of the parasitic PNP 139 is too high, especially in the case of lightly-doped shallow N-wells, bipolar snapback breakdown (also known as BVceo or BVcer breakdown) may result and the device may be damaged or destroyed. Without isolation, it is difficult to control the characteristics of parasitic PNP 139 without affecting the other characteristics of MOSFET 132, such as its threshold voltage.
N-channel MOSFET 131, with its source-to-body junction schematically represented by P-N diode 133; and drain-to-body junction represented by P-N diode 134, has its body shorted to the substrate, represented here by the ground symbol, and therefore is not isolated. Resistance of the P-well and surrounding P-type substrate region is illustrated as a lumped-circuit-element resistance 135, which in reality is spatially distributed across the device and the substrate, especially for large area power devices. Aside from the circuit implications of a grounded body connection, the forward biasing of drain diode 134 injects electrons into the P-type substrate which may travel considerable distances across an integrated circuit (chip) before recombining or being collected. Such parasitic ground currents can adversely impact other devices and impair proper circuit operation.
Since most CMOS pairs are used in digital circuits as logic gates (like inverter 150 in FIG. 3C) parasitic diodes 154 and 153 remain reverse biased for all operating conditions of N-channel 151 and P-channel 152 normally encountered. If the same inverter, however, were used to drive an inductor in a Buck switching regulator, diode 153 will become forward-biased whenever P-channel 152 turns off, injecting current into the substrate and potentially causing unwanted phenomena to occur.
A similar problem occurs when using non-isolated CMOS for implementing cascode clamped output driver 160 shown in FIG. 3D. In this circuit, the output voltage of the inverter comprising N-channel 161 and P-channel 163 is clamped to some maximum positive voltage by the N-channel follower 162 which limits the output voltage to one threshold voltage VTN(162) below its gate bias Vbias. Through its cascode action the inverter is able to reduce, i.e. “level shift”, its output to a smaller voltage range than the supply voltage Vcc. Diodes 164, 165, 166, and 167 all remain reverse biased during normal operation. The problem is that since diode 166 is reverse-biased to a voltage equal to Vout, the threshold of N-channel 162 increases in proportion to the output voltage and thereby limits the circuit's maximum output voltage. If N-channel MOSFET 162 were isolated, its source and body could be shorted to the output, so that diode 166 would never be reverse-biased and its threshold voltage would remain constant.
Junction-Isolated CMOS Fabrication and Construction
The need for electrically isolated CMOS is further exemplified in circuit 150 of FIG. 4A, where a pair of N-channel MOSFETs 151 and 152 are connected in a totem pole configuration and driven out of phase by break-before-make (BBM) circuit 155. To achieve a low on-resistance independent of its operating condition, high side N-channel MOSFET 152 requires a source-body short (so that VSB=0 at all times). Floating bootstrap capacitor 157 powers floating gate drive circuitry 156 to provide adequate gate bias VGS for MOSFET 152, even when the high-side device is on and Vout is approximately equal to Vcc. To implement the bootstrap drive, both floating circuit 156 and high-side MOSFET 152 must be electrically isolated from the IC's substrate (i.e. ground).
Another circumstance requiring isolation is illustrated in Buck converter 170 of FIG. 4B, where a push-pull CMOS pair including a low-side MOSFET 171 and a high-side MOSFET 172 controls the current in inductor 177 and in closed loop operation, regulates a constant voltage across output capacitor 178. While diode 173 anti-parallel to high-side MOSFET 172 remains reverse-biased during normal operation, drain-to-body diode 174 of low-side MOSFET 171 does not remained reverse-biased. Each time high-side MOSFET 172 is turned off; inductor 177 drives the inverter output voltage Vx below ground forward-biasing diode 174. If conduction current in the MOSFET's body is sufficient to develop a voltage drop across resistance 175, electrons may be injected deep into the substrate via the bipolar transistor action of parasitic NPN 176 and may be collected by any other N region 179. The resulting substrate current can adversely affect efficiency, and cause circuit malfunction. If the low-side MOSFET 175 were isolated, the diode current could be collected without becoming unwanted substrate current.
The most common form of complete electrical isolation is junction isolation. While not as ideal as dielectric isolation where oxide surrounds each device or circuit, junction isolation has to date offered the best compromise between manufacturing cost and isolation performance. As shown in FIG. 5A, the prior art CMOS isolation requires a complex structure comprising N-type epitaxial layer 203 grown atop a P-type substrate 201 and surrounded by an annular ring of deep P-type isolation PISO 204 electrically connecting to the P-type substrate to completely isolate an N-type epitaxial island by P-type material below and on all sides. Growth of epitaxial layer 203 is also slow and time consuming, representing the single most expensive step in semiconductor wafer fabrication. The isolation diffusion is also expensive, formed using high temperature diffusion for extended durations (up to 18 hours). To be able to suppress parasitic devices, a heavily doped N-type buried layer NBL 202 must also be masked and selectively introduced prior to epitaxial growth.
To minimize up-diffusion during epitaxial growth and isolation diffusion, a slow diffuser such as arsenic (As) or antimony (Sb) is chosen to form NBL 202. Prior to epitaxial growth however, this NBL layer must be diffused sufficiently deep to reduce its surface concentration, or otherwise the concentration control of the epitaxial growth will be adversely impacted. Because the NBL layer is comprised of a slow diffuser, this pre-epitaxy diffusion process can take more than ten hours.
Once isolation is complete CMOS fabrication can commence in a manner similar to the aforementioned discussion. Referring again to FIG. 5A, P-well 205 and N-well 206 are implanted and diffused to facilitate N-channel and P-channel fabrication. Since they are formed in an isolated epitaxial pocket of N-type silicon however, they advantageously are completely isolated from the substrate.
Since junction isolation fabrication methods rely on high temperature processing to form deep diffused junctions and to grow epitaxial layers, these high temperature processes are expensive and difficult to manufacture, and are incompatible with large diameter wafer manufacturing, exhibiting substantial variation in device electrical performance and preventing high transistor integration densities. The complexity of junction isolation is illustrated in flowchart 220 of FIG. 5B. After all the steps shown are performed, the wafer must proceed to the formation of a field oxide layer, and only then may the extensive CMOS manufacturing portion of the flow begin.
Another disadvantage of junction isolation is the area wasted by the isolation structures and otherwise not available for fabricating active transistors or circuitry. In FIG. 5C, the area needed to satisfy certain minimum design rules is illustrated for a buried layer 212, P-type diffused junction isolation 213, and a diffused heavily doped N-type sinker 214 (overlapping onto NBL 212B). As a further complication, with junction isolation the design rules (and the wasted area) depend on the maximum voltage of the isolated devices. For an epitaxial layer grown to a thickness xepi, the actual thickness supporting voltage xnet is less since the depth of P+junction 216 and the up-diffusion of NBL 212A must be subtracted from the total thickness to determined the voltage capability of the isolated devices.
Common epitaxial thicknesses range from 4 microns to 12 microns. The required opening for the isolation region implant depends on the epitaxial thickness being isolated. The PISO mask opening must be sufficiently large to avoid starved diffusion effects. A starved diffusion occurs when two-dimensional (or three-dimensional) diffusion reduces the dopant concentration gradient and slows the vertical diffusion rate. In fact unless the PISO opening is sufficient, the isolation may not even reach the substrate. As a general rule of thumb to avoid starved diffusion, the opening for the isolation implantation should have a dimension y1 approximately equal to the epitaxial thickness xepi.
Ignoring two-dimensional effects, during the isolation drive-in cycle, lateral diffusion occurs at a rate approximately 80% that of the vertical (per side). So the actual surface width of a diffused isolation y2 is approximately equal to [xepi+2·(0.8·xepi)]=2.6·xepi Using this guideline, isolating a 7 micron epitaxial layer requires an 18 micrometer wide isolation ring. Further spacing y6 must be included to prevent avalanche breakdown between the bottom of isolation 213 and NBL 212A.
Similar design rules must be considered for fabricating a diffused low-resistance sinker 214 for connecting NBL layer 212B to the surface. The Nsinker mask opening must have a dimension y3 approximately equal to its depth xnet. This results in a sinker surface width y4 equal to [xnet+2·(0.8·xnet)]=2.6·xnet. Assuming that xnet=5 microns (for a 7 micron epitaxial layer), then the sinker ring has a surface width of 13 micrometers. Allowing 2 micrometers of space y5 between the isolation and sinker rings means the surface area required for a sinker and an adjacent isolation is [y2+y5+y4]=[18+2+13] or 33 micrometers. Obviously, conventional epitaxial junction isolation, despite its electrical benefits, is too area wasteful to remain a viable technology option for mixed signal and power integrated circuits.
An Epiless Fully-Isolated BCD Process with Contouring Implants
As disclosed in U.S. Pat. No. 6,855,985, issued Feb. 15, 2005, entitled “Modular Bipolar-CMOS-DMOS Analog Integrated Circuit & Power Transistor Technology,” by Richard K. Williams, et. al., incorporated herein by reference, a fully-isolated process integrating CMOS, bipolar and DMOS transistors can be achieved without the need for high temperature diffusions or epitaxy. As illustrated in the multi-voltage CMOS 250 of FIG. 6, the principal of the previously disclosed modular BCD process relies on high-energy (MeV) ion implantation through contoured oxides to produce self-forming isolation structures with virtually no high temperature processing required. This low-thermal budget process benefits from “as-implanted” dopant profiles that undergo little or no dopant redistribution since no high temperature processes are employed.
In the structure shown, deep N-type layers (DN) 253A and 253B, implanted through LOCOS field oxide layer 255, form a conformal isolation structure that encloses multi-voltage CMOS. For example, DN layer 253A contains 5V CMOS wells comprising a surface P-well 255 (PW1) with a more highly concentrated buried P-well 254 (PW1B), and a surface N-well 253 (NW1) with a more highly concentrated buried N-well 252 (NW1B), with doping profiles optimized for 5V N-channel and P-channel MOSFETs. In another region on the same die DN layer 253B contains 12V CMOS wells comprising a surface P-well 259 (PW2) with a more highly concentrated buried P-well 258 (PW2B), and a surface N-well 257 (NW2) with a more highly concentrated buried N-well 256 (NW2B), with doping profiles optimized for 12V N-channel and P-channel MOSFETs. The same process is able to integrated bipolar transistors, and a variety of power devices, all tailored using conformal and chained ion implantations of differing dose and energy. (Note: As used herein, the term “conformal” refers to a region or layer of dopant (a) that is formed by implantation through a layer (often an oxide layer) at the surface of the semiconductor material, and (b) whose vertical thickness and/or depth in the semiconductor material vary in accordance with the thickness and/or other features of the surface layer, including any openings formed in the surface layer.)
While this “epi-less” low thermal budget technique has many advantages over non-isolated and epitaxial junction isolated processes, its reliance on LOCOS imposes certain limitations on its ability to scale to smaller dimensions and higher transistor densities. The principal of conformal ion implantation in the LOCOS based modular BCD process is the concept that by implanting through a thicker oxide layer dopant atoms will be located closer to the silicon surface and by implanting through a thinner oxide layer, the implanted atoms will be located deeper in the silicon, away from the surface.
The scaling problem of conformal implantation is illustrated in FIG. 7. With LOCOS 282 as shown in FIG. 7A, the natural slope of the bird's beak region creates a smooth continuous gradation in oxide thickness that is mirrored by a smooth continuous gradation 285 in the depth of the implanted DN layer. The floor isolation region 284 sets the one-dimensional device characteristics, but the isolation sidewall is self forming, tapering toward the surface to the right of line 287 as the oxide thickness 286 increases. No implant is introduced through photoresist mask layer 283.
But to improve CMOS transistor integration density, the bird's beak taper must be reduced into a more vertical structure so that the devices can placed more closely for higher packing densities. For example, in FIG. 7B, the bird's beak region 296 to the right of line 297 is much steeper. The result is a greater portion of the implant is uniformly touching the bottom of LOCOS 292, and the transition 295 between the deep portion 294 and the field area 298 is more vertical and more abrupt. As a result, the width of the isolation for sidewall portion 295 is narrowed and the isolation quality is sacrificed.
To make the point more extreme, FIG. 7C illustrates a nearly vertical oxide profile for LOCOS 302, where the graded portion 306 to the right of line 307 is very is very short. The resulting implant profile shows a very thin abrupt transition 305 between the deep isolation 304 and the surface doping 308. Hence, there is a conflict. Region 305 is too narrow to provide good isolation yet only by making a steeper oxide can more transistors be packed into the same real estate.
What is needed is a new isolation structure that provides complete electrical isolation and high density integration without the use of epitaxial layers or long, high-temperature processes.